I'm a Verification Engineer currently working at Siemens EDA (formerly Mentor Graphics), with an experience of 2+ years. I have done my Bachelors in Technology(Electronics) from Manav Rachna University with a CGPA of 9.14. I have strong knowledge of SystemVerilog, Verilog, UVM and RISC-V ISA. I have worked on the development of AMBA AXI 5/4/4-Lite/3, AXI4Stream, AHB, TileLink, MIPI DSI2 and USB (3.0/3.1/3.1 Re-Timer) Verification IP's. I have also worked on verification of RISC-V Instruction Cache IP.
My CV.